1. Field of the Invention
The present invention relates to a multiprocessor system which is provided with a plurality of printed circuit boards for power-on reset of processors when the power is turned on.
Generally, in the case of driving a processor, the reset processing is executed for initializing programs so that each of the programs is executed correctly when the power is turned on.
Particularly, each processor must be reset simultaneously in the multiprocessor system which executes the one process with a plurality of processors by respectively providing the processors in an of processing function.
2. Description of the Prior Art
FIG. 1 to FIG. 3 show a structure of a multiprocessor system of the prior art. FIG. 1 is a structure providing a plurality of processors in a single printed circuit board. The printed circuit board 1 is provided with processors 2.sub.1, 2.sub.2.
Both processors 2.sub.1, 2.sub.2 are respectively provided with a power supply voltage monitor circuit 3 to supply the power-on reset signal. Upon detection of 5V power supply voltage, the power supply voltage monitor circuit 3 outputs a reset signal. The processors 2.sub.1, 2.sub.2 are reset with the power-on reset signal of the power supply voltage monitor circuit 3.
The structure shown in FIG. 1 has a plurality of processors on one printed circuit board. Namely, a plurality of processors operate with a common power supply. Therefore, the printed circuit board is provided with only one power supply voltage monitor circuit. This monitor circuit supplies the power-on reset signal to each processor when the power is turned ON.
This structure is effective for executing simple processing with the multiprocessor. However, the structure which carries out complicated processing requires many input/output circuits in the periphery of processors. Therefore, provision of many processors on one printed circuit board results in problems.
FIG. 2 and FIG. 3 show the structure providing the processors on a plurality of printed circuit boards.
In FIG. 2, 4.sub.1 and 4.sub.2 designate printed circuit boards and these are connected with a connector 5.
The processor 6 and power supply voltage monitor circuit 7 are provided on the printed circuit board 4.sub.1, while the processor 6.sub.2 is provided on the printed circuit board 4.sub.2.
Here, when the power supply is turned on for the printed circuit boards 4.sub.1 and 4.sub.2, the power supply voltage monitor circuit 7 detects a supply of power source voltage and outputs the reset signal. With the reset signal of the power supply voltage monitor circuit 7, the processor 6.sub.1 is power-on reset and the processor 6.sub.2 is also power-on reset through a connector 5.
As shown in FIG. 2, the structure where a plurality of processors are reset by the power supply voltage monitor circuit 7 provided on one printed circuit board has merit in that a plurality of processors are reset simultaneously. However, when power is turned on while a fault is generated in the connector connecting the printed circuit boards, only one printed circuit board is reset and the other processors are not reset.
As explained above, here rises a problem that the system as a whole operates without control because the other processors are not reset.
FIG. 3 indicates a structure that the printed circuit board 8.sub.1 is provided with the power supply voltage monitor circuit 10.sub.1 and the processor 9.sub.1. The printed circuit board 8.sub.2 is also provided with the power supply voltage monitor circuit 10.sub.2 and processor 9.sub.2.
In such a structure, when the power supplies of printed circuit boards 8.sub.1 and 8.sub.2 are turned on, the power supply voltage monitor circuit 10.sub.1 provided on the printed circuit board 8.sub.1 power-on resets the processor 9.sub.1 provided on the same printed circuit board 8.sub.1.
In the same way, the power supply voltage monitor circuit 10.sub.2 provided on the printed circuit board 8.sub.2 power-on resets the processor 9.sub.2 provided on the same printed circuit board 8.sub.2.
In FIG. 3, each of the power supply voltage monitor circuits outputs a reset signal at a different timing because a voltage level of each printed circuit board becomes stable at a different time. When the power is turned on, a deviation of power-on timing for all processors occurs. It is therefore no longer possible to simultaneously reset the processors 9.sub.1 and 9.sub.2.
Therefore, the system employing the multiprocessor structure noted above results in a problem that the processor process cannot be realized stably.
The structure of FIG. 1 also results in a problem that the structure of the printed circuit board becomes large because a plurality of processors for different functions are accommodated on the one printed circuit board.
On the other hand, the structure of FIG. 2 does not result in a problem that the structure of the printed circuit board becomes large, because only one processor is provided on the one printed circuit board.
However, this structure results in a problem that sometimes occurs that the reset signal from the power supply voltage monitor circuit is not reset if connection between the printed circuit boards is bad in the printed circuit board that is not providing the power supply voltage monitor circuit.
Unlike the case where reset is not carried out as shown in FIG. 2 because connection between the printed circuit boards is not related, the structure of FIG. 3 results in a problem that if power-on timing deviates, the processors 9.sub.1 and 9.sub.2 are no longer reset simultaneously.